The present invention relates to a gate array semiconductor integrated circuit having a memory function and a manufacturing method applicable to a semiconductor integrated circuit for data processing.
The gate array method may be employed to more cheaply manufacture various kinds of semiconductor integrated circuits in small quantities in a short period of time. The gate array method is designed to obtain a semiconductor integrated circuit having a desired individual function by providing a diffused wafer (diffused gate array wafer), having basic cells disposed on a semiconductor substrate with cell-to-cell wiring in accordance with user specification by means of an individual mask pattern. There has developed a demand for the gate array having logical cells such as gates and flip flops to be provided with a memory function such as a RAM (Random Access Memory) and a ROM (Read Only Memory) as integration and circuit scale therein increase. Although it is possible to form a memory structure by utilizing the logical cell such as latching in the gate array, this method of forming a large scale memory is disadvantageous in that production efficiency is extremely deteriorated. This gate array semiconductor integrated circuit may include a memory such as dynamic RAM. According to the art described in CICC (Custom Integrated Circuits Conference) issued by IEEE, 1988, for instance, a gate array semiconductor integrated circuit may contain dynamic RAM having a capacity of 1 Mbit. The dynamic RAM in this case is designed to input and output data on an 8-bit basis.